Precision high-frequency capacitor on semiconductor substrate

ABSTRACT

A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This invention is related to application Ser. No. 09/545,287 byKasem et al., filed Apr. 7, 2000, entitled “Vertical Structure AndProcess For Semiconductor Wafer-Level Chip Scale Packages”, which isincorporated herein by reference in its entirety.

FIELD OF THE INVENTION

[0002] This invention relates to semiconductor technology and inparticular to the formation of a high-frequency capacitor on asemiconductor substrate.

BACKGROUND OF THE INVENTION

[0003] Higher frequencies are increasingly being used in communicationstechnology. For example, frequencies in the range of 450 MHz to 3 GHzare used in cellular communications and frequencies in the range of 10GHz to 18 GHz are used in satellite video and data transmission.

[0004] These applications require small, precise capacitors. Multi-layerceramic capacitors have been employed for this purpose, but they tend tobe lacking in precision and performance. Thin film capacitors haveimproved precision and performance but they are expensive.

[0005] Accordingly, there is a need for a precision high-frequencycapacitor that can be manufactured at a reasonable cost.

SUMMARY OF THE INVENTION

[0006] In accordance with this invention, a precision high-frequencycapacitor is formed on a heavily-doped semiconductor substrate havingfirst and second principal surfaces. The capacitor includes a dielectriclayer on the first principal surface of the substrate and a mainelectrode layer on the dielectric layer. A conductive layer is formed onthe second principal surface of the substrate. A via containing aconductive material extends through the substrate. A second electrodelayer is formed over the first principal surface of the substrate,adjacent an opening of the via. The second electrode is electricallyconnected to the conductive layer by means of the conductive material inthe via. Thus, when a voltage difference is applied to the electrodes,the main electrode layer and the substrate act as the “plates” of thecapacitor, separated by the dielectric layer.

[0007] In an alternative embodiment, the via is omitted, and the secondelectrode layer, electrically insulated from the first electrode layer,is formed over the first principal surface of the substrate. In oneversion, the second electrode is separated from the substrate by thedielectric layer, creating in effect a pair of series-connectedcapacitors, with the substrate representing the common terminal betweenthe capacitors. In another version, the second electrode is inelectrical contact with the substrate, creating a single capacitor. Eachof the electrode layers may include a plurality of fingers, with thefingers being interdigitated. The dielectric layer, often an oxide, maybe thinner under the fingers than under the “palm” portions of theelectrode layers from which the fingers protrude.

[0008] Capacitors in accordance with this invention exhibit numerousadvantages as compared with prior art capacitors. They can be fabricatedat a wafer level with a very low effective series resistance (ESR). Theycan function at very tight tolerances (e.g., <2%) throughout theiroperational range and can operate at very high frequencies (e.g., up to5 GHz and higher). They can have a quality (Q) factor, for example, thatis much higher than 1000 at 1 MHz.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] This invention will be best understood by reference to thefollowing drawings, in which like components have the same referencenumeral. The drawings are not necessarily drawn to scale.

[0010]FIG. 1 is a cross-sectional view of a capacitor in accordance withthe invention containing a via through the substrate.

[0011]FIG. 1A is a graph showing the Q of a capacitor in accordance withthis invention, i.e., the ratio of the imaginary part of the impedanceto the real part of the impedance, as a function of frequency.

[0012] FIGS. 2A-2J illustrate the steps of a process that can be used tofabricate the capacitor of FIG. 1.

[0013]FIG. 3 is a cross-sectional view of a capacitor in accordance withthis invention containing two electrodes on the same surface of thesubstrate.

[0014]FIG. 4 is a cross-sectional view of a capacitor with trenchesformed under each of the electrodes.

[0015]FIG. 5 is a cross-sectional view of a capacitor similar to thecapacitor shown in FIG. 3 except that one of the electrodes iselectrically connected to the substrate.

[0016]FIG. 6 is a top view of a capacitor wherein the electrodes havefingers interdigitated with each other.

[0017]FIG. 7 is a cross-sectional view of the capacitor shown in FIG. 6showing that the dielectric layer is thinner under the fingers.

[0018]FIG. 8 is a circuit diagram of an ESD-protected capacitorcontaining a pair of oppositely-directed diodes.

[0019]FIG. 9 is a cross-sectional view of an ESD-protected capacitor inaccordance with this invention.

[0020]FIGS. 10a and 10 b are graphs showing simulated breakdowncharacteristics of an ESD-protected capacitor of the kind shown in FIG.9.

[0021]FIG. 11 is a graph showing the simulated effective capacitance ofthe ESD-protected capacitor.

DESCRIPTION OF THE INVENTION

[0022] The principles of this invention will be described by referenceto the following embodiments, which are illustrative only.

[0023]FIG. 1 shows a cross-sectional view of a first embodimentaccording to the invention. Capacitor 10 is formed on an N+ siliconsubstrate 102. Substrate 102 may be doped to a concentration of 3 to4×10¹⁹ cm⁻³, for example, and may have a resistivity of about 2 mΩ-cmand as high as about 3 mΩ-cm. A dielectric layer 104 is formed on thefront surface of substrate 102. Dielectric layer 104 is formed of SiO₂,which may be thermally grown or deposited by chemical vapor deposition(CVD). Alternatively, layer 104 could be formed of another dielectricsuch as a nitride or a combination of an oxide and a nitride. Athermally-grown oxide is reliable and reproducible and can withstandelectric fields up to 4 MV/cm without deterioration. The 3 σ variabilityof the thickness of a thermally-grown oxide thicker than 0.1 μm is lessthan 1.5%. On top of dielectric layer 104 is a main electrode 106 and asecond electrode 108. Electrodes 106 and 108 can be a single- ormulti-layer structure, and can be made of doped polysilicon, arefractory metal, a refractory metal suicide, an aluminum-based alloy,copper or combination of the foregoing materials. If they are formed ofmetal, electrode 106 may include a “seed” or “barrier” layer of a metal(e.g., Ta/Cu) deposited on substrate 102 by sputtering or evaporation,overlain by a plated layer. Electrodes 106 and 108 are covered by aninsulating passivation layer 110. Openings are formed in passivationlayer 110, and solder balls 112 and 114 are deposited the openings toallow electrical contact to be made to the electrodes 106 and 108.

[0024] Beneath the second electrode 108, a via or through-hole 116 isformed through N+ substrate 102. A conductive material 118 such asaluminum or copper fills the via 116. The conductive material 118contacts a conductive layer 120 which is formed on the back side ofsubstrate 102. Conductive layer 120 may include a metal seed layerdeposited on substrate 102 by sputtering or evaporation, overlain by aplated metal layer.

[0025] Capacitor 10 thus includes a first “plate” represented by mainelectrode 106, which is contacted via solder ball 112; and a second“plate” represented by N+ substrate 102, which is contacted via solderball 114, second electrode 108, conductive material 118 and conductivelayer 120. The “plates” are separated by dielectric layer 104.

[0026] The thickness of dielectric layer 104 can be in the range of 50 Åto 2 μm. The thinner dielectric layer 104 is, the higher thecapacitance. On the other hand, the thinner dielectric layer 104 is, thelower the maximum voltage that capacitor 10 can be exposed to withoutdamaging dielectric layer 104. For example, if dielectric layer 104 isan oxide having a thickness of 0.1 μm, capacitor 10 would have acapacitance of roughly 350 pF/mM².

[0027] Silicon substrate 102 can have a thickness of 200 μm or less.Doping substrate 102 to a concentration higher than 1×10¹⁹ cm⁻³ keepsthe effective series resistance (ESR) at a low level and avoids theformation of a depletion layer in the substrate. For example, the ESRfor a silicon substrate doped to a concentration of 2×10¹⁹ cm⁻³ was only2.4 mΩmm².

[0028] In addition, it is desirable that the Q factor of the capacitorbe higher than 1000 at 1 MHz. The Q factor is defined by the followingequation: $Q = \frac{X_{C}}{R_{S}}$

[0029] where X_(C) is the impedance and R_(S) is the series resistanceof the capacitor at a particular frequency.

[0030]FIG. 1A is a plot of X_(C) and R_(S) as a function of frequencyfor capacitor 10, described above, wherein the thickness of the oxidedielectric layer 104 is 0.1 μm and the N+ silicon substrate is doped to2×10¹⁹ cm⁻³. As shown, the Q factor of the capacitor is higher than 100up to a frequency of about 2 GHz and is greater than 1000 at 100 Mhz.

[0031] While capacitor 10 can be fabricated by a number of processes,FIGS. 2A-2J illustrate the steps of one process that may be used.

[0032] As shown in FIG. 2A, the process begins with N+ silicon substrate102. Preferably, substrate 102 is one die of a wafer that will beseparated from the other dice at the completion of the process.Substrate 102 may or may not include an epitaxial layer.

[0033] Dielectric layer 104 is formed by growing an oxide (SiO₂) layerthermally on the front (top) surface of substrate 102. For example, a0.2 μm thick oxide layer can be grown by heating the substrate to 1100°C. for 6 minutes in a wet atmosphere.

[0034] Referring to FIG. 2B, a barrier layer 202 of Ta/Cu is sputteredover the entire surface of oxide layer 104. Layer 202 can be 0.5 to 1.0μm thick, for example. A photoresist layer 204 is deposited andpatterned as shown in FIG. 2B to define where the main electrode will belocated.

[0035] A copper layer 206 is plated onto the exposed portions of Ta/Culayer 202, and photoresist layer 204 is removed, leaving the structureshown in FIG. 2C.

[0036] The front side of substrate 102 is then taped or otherwisesupported, and substrate 102 is thinned from the back side. Substrate102 may be thinned by grinding its back side. Alternatively, otherthinning techniques such as wet etching and vacuum plasma etching can beused to thin substrate 102. Another possibility is the atmosphericdownstream plasma (ADP) plasma etching system available from Tru-SiTechnologies, Inc. of Sunnyvale, Calif. Substrate 102, which caninitially be in the range of 625 μm thick, can be thinned to a thicknessof less than 200 μm, for example.

[0037] After the thinning process has been completed, the tape or othersupport is removed. A layer 208 of Ta/Cu is sputtered or evaporated overthe entire back side surface of substrate 102, and a copper layer 210 isplated onto Ta/Cu layer 208, leaving the structure shown in FIG. 2D.Copper layer 210 can be 2-3 μm thick, for example.

[0038] As shown in FIG. 2E, a photoresist layer 212 is deposited on thefront side of silicon substrate 102. Photoresist layer 212 is patternedand etched to produce an opening 214. A conventional wet etch processcan be used, for example. Silicon substrate 102 is etched throughopening 214 to form a via 216 and thereby expose the surface of barrierlayer 208. As shown in FIG. 2E, via 216 is conical in shape becausesilicon etches along oblique planes. Depending on the shape of opening214, via 216 could be any shape.

[0039] As shown in FIG. 2F, photoresist layer 212 is then removed, and aseed layer 218 of Ta/Cu is sputtered onto the entire front side surfaceof the structure. Ta/Cu layer 218 can be 0.5-1.0 μm thick, for example.

[0040] As shown in FIG. 2G, a photoresist layer 220 is deposited andpatterned, leaving a portion of the Ta/Cu layer 218 in the vicinity ofthe via 216 exposed.

[0041] As shown in FIG. 2H, a copper layer 222 is plated onto theexposed portions of Ta/Cu layer 218, filling via 216 and overflowingonto the surface of substrate 102.

[0042] As shown in FIG. 2I, photoresist layer 220 is removed and Ta/Culayer 218 is etched, leaving the copper layer 222 in place.

[0043] As shown in FIG. 2J, a passivation layer 224 is formed andpatterned over the surface of the structure by screen printing, withopenings that expose portions of copper layers 206 and 222. Solder bumps226 and 228 are formed on the exposed portions of copper layers 206 and222. The result is capacitor 10 shown in FIG. 1, which can be mounted ona printed circuit board (PCB) or other structure, using flip-chipmounting techniques. Optionally, a second passivation layer 230 can beformed on the back side of the structure.

[0044] Capacitor 10 is preferably formed along with other similarcapacitors on a single wafer. If so, following the fabrication of thecapacitors, the die which contains capacitor 10 is separated from theother dice in the wafer by sawing the wafer along the scribe lines.

[0045]FIG. 3 shows a cross-sectional view of an alternative embodiment.Capacitor 30 is actually a pair of capacitors connected in series. Adielectric layer 302 is formed on N+ silicon substrate 102. Substrate102 could have a doping concentration of 2×10¹⁹ cm⁻³, for example, andlayer 302 could be thermally-grown oxide with a thickness of 0.1 μm. Ametal layer is deposited on dielectric layer 302 and is patterned, usingnormal photolithographic processes, to form a first electrode 304 and asecond electrode 306. A passivation layer 308 is deposited on the topsurface of the structure. Openings are formed in passivation layer 308,and solder balls 310 and 312 are formed as described above.

[0046] While capacitor 30 is simpler and less expensive to fabricatethan, for example, capacitor 10 (FIG. 1), its capacitance is lower andits series resistance is greater. For example, the effective capacitanceper unit area is up to 4 times smaller than that of a verticalstructure. The series resistance increases with the square of thelateral dimension of the device.

[0047] The capacitance per unit area of capacitor 40, shown in FIG. 4,is significantly increased by the formation of trenches 406 underelectrodes 304 and 306. Dielectric layer 402 extends into trenches 304and 306 and lines the walls thereof in the manner of a normaltrench-gated MOSFET. Trenches 304 and 306 are filled with a conductivematerial 404, such as polysilicon, which is in electrical contact withelectrodes 304 and 306. The net result is to increase the effective areaof the interface between the “plates” and the dielectric layer of thecapacitor.

[0048]FIG. 5 shows a cross-sectional view of a capacitor 50 which issimilar to capacitor 30 shown in FIG. 3 except that the electrode 504 isin electrical contact with the N+ substrate 102. Electrode 502 isseparated from substrate 102 by a dielectric layer 506 having a definedthickness. Capacitor 50 has a capacitance value per unit area similar tothat of capacitor 10 shown in FIG. 1. However, the lateral placement ofelectrodes 502 and 504 leads to a larger effective series resistance(ESR) which is a function of the lateral dimension of the device.

[0049]FIG. 6 is a top view of a capacitor 60 in which the firstelectrode 602 has fingers 602 a-602 c that are interdigitated withfingers 604 a-604 d of the second electrode 604. FIG. 7 is across-sectional view taken at cross-section 7-7 shown in FIG. 6 (notethat the scales of FIGS. 6 and 7 are not the same). In an active region606, where the fingers are interdigitated, a thin dielectric layer 618is formed over the substrate. A relatively thick dielectric layer 614separates the remaining “palm” portion of electrode 602 from N+substrate 102, and a relatively thick dielectric layer 616 separates thepalm portion of electrode 604 from substrate 102.

[0050] The capacitance of capacitor 60 is determined by the number anddimensions of the fingers. As indicated in FIG. 6, electrode 604 can beseparated from the N+ substrate by a dielectric layer, creating a pairof capacitors, or it can be in direct electrical contact with the N+substrate (in the manner of electrode 504 in FIG. 5), creating a singlecapacitor. In many embodiments, the pitch “p” of the finger layout willbe less than 300 μm. For example, a capacitor 60 wherein electrode 604is in direct electrical contact with the substrate and the pitch of theinterdigitated fingers is 250 μm (finger width of 200 μm, spacing of 50μm) and the thin dielectric layer 618 is a 0.1 μm-thick oxide layer, hasa capacitance of 150 pF/mm² and an ESR of 12 mΩ mm².

[0051] The thin dielectric layers used in precision capacitors makethese devices very susceptible to damage from electrostatic discharges(ESDs). For example, ESDs can be generated by handling during theassembly process. One way to protect against ESDs is to connect a pairof oppositely-directed Zener diodes D1, D2 in parallel with thecapacitor, as shown in the circuit diagram of FIG. 8. When an ESDvoltage spike occurs, one of the diodes conducts in the forwarddirection and the other diode breaks down at a predetermined voltage andconducts in the reverse direction, thereby providing a current patharound the capacitor. The voltage at which current flows in theprotective path is equal to the reverse breakdown voltage of one diodeplus the voltage at which the other diode conducts in the forwarddirection (typically about 0.5 V). (As used herein, the term“oppositely-directed” means that the diodes are connected in series witheither their anodes facing each other or their cathodes facing eachother, such that any current in the series path flows through one of thediodes in the forward direction and through the other diode in thereverse direction.)

[0052] In accordance with an aspect of this invention, the protectivediodes can be formed in the substrate itself, as shown in theESD-protected capacitor arrangement of FIG. 9. An N+ region 902, a Pregion 904 and an N+ region 906 are formed in substrate 102 beneathelectrode 106. The regions are formed such that there is a first PNjunction between N+ region 902 and P region 904 that represents one ofthe diodes and a second PN junction between P region 904 and N+ region906 that represents the other diode. The doping concentrations ofregions 902, 904 and 906 are set such that the PN junctions break downin the reverse direction at a desired voltage. The breakdown voltagedepends on the doping concentration on the more lightly doped side ofthe PN junction and other factors that are well-known in the art. See,for example, Sze, Physics of Semiconductor Devices, 2^(nd) Ed., JohnWiley & Sons (1981), pp. 99-108, which is incorporated herein byreference.

[0053] The second N+ region 906, which extends into the P region 904 aswell as the N+ substrate, is used to provide a symmetrical breakdowncharacteristic of the diode pair. In some embodiments, N+ region 906 maybe omitted.

[0054] To maintain the high RF performance capabilities of thecapacitor, the impedance of the Zener diodes can be set at a level thatis higher than the capacitor by a factor of 1000 or more.

[0055] Processes for forming the diodes in the substrate are well knownto those skilled in the art. One such process is as follows:

[0056] 1. Initially, an N-type epitaxial (epi) layer that is 2.5 μmthick is formed on the top surface of the substrate. The dopingconcentration of the epi layer is 1×10¹⁶ cm⁻³, far less than that of theunderlying portion of the substrate.

[0057] 2. A first photoresist mask with an opening defining the activearea where the capacitor will be located is formed over the epi layer,and phosphorus is implanted through the opening in the mask at a dose of8×10¹⁵ cm⁻² and an energy of 80 keV to set the doping concentration ofthe epi layer to approximately the same level as the rest of the N+substrate (10¹⁹ cm⁻³). The first mask is then removed.

[0058] 3. After the phosphorus implant into the active area through thefirst mask, another mask is formed over the substrate with an openingdefining where P region 904 will be located. Boron is implanted throughthe opening in this mask, for example, at a dose of 2×10¹³ cm⁻² and anenergy of 80 keV, to form P region 904.

[0059] 4. The substrate is annealed at 1150° C. for 30 minutes to drivethe phosphorus and boron implants through the epi layer.

[0060] 5. The oxide dielectric layer 104 is thermally grown as describedabove.

[0061] 6. After the oxide layer has been grown, a third photoresist maskis formed on the oxide layer and patterned to create openings whichdefine the-N+ regions 902 and 906.

[0062] 7. The oxide layer is partially etched through the openings inthe third photoresist mask to avoid the need to implant dopant through athick oxide film.

[0063] 8. Phosphorus is then implanted through the openings in the thirdmask and the thinned oxide layer at, for example, a dose of 3×10¹⁵ cm⁻²and an energy of 60 keV to form N+ regions 902 and 906.

[0064] 9. The third photoresist mask is removed, and a blanket boronimplant is performed through the oxide layer to set a surface doping ofthe P-well. This can be done, for example, at a dose of 3×10¹² cm⁻² andan energy of 60 keV. The boron dopant can be activated by annealing at950° C. for 30 minutes in an oxidizing ambient.

[0065] 10. A fourth photoresist mask is formed and patterned with anopening over the area where contact is to be made to the N+ region 902.The oxide layer is etched through the opening to expose N+ region 902.The fourth mask is then removed.

[0066] Following this, the process described above continues with theformation of the electrodes 106 and 108.

[0067] Numerical simulations were done to calculate the performance ofthe ESD-protection structure shown in FIG. 9. The dimensions of thestructure were as follows: Width (W1) of P region 904: 5 μm Width (W2)of N+ region 902: 3 μm Length of structure: 100 μm

[0068]FIG. 10a shows the IV characteristic of the structure withelectrode 106 biased positive with respect to electrode 114(“accumulation bias”), and FIG. 10b shows the IV characteristic of thestructure with electrode 106 biased negative with respect to electrode114 (“depletion bias”). As indicated, the diode pair breaks down in therange of 16-19 V in either direction. FIG. 11 shows that the effectivecapacitance of the combined capacitor and ESD-structure remains quiteconstant at about 0.15 pF throughout the frequency range from 0.1 to 10GHz.

[0069] The embodiments of this invention described above are onlyillustrative, and not limiting. Numerous alternative embodiments will beapparent to persons skilled in the art from the above description.

We claim:
 1. A precision high-frequency capacitor comprising: aheavily-doped semiconductor substrate having first and second principalsurfaces; a dielectric layer formed on the first principal surface ofthe substrate; a main electrode layer formed on the dielectric layer; aconductive layer formed on the second principal surface of thesubstrate; a via extending through the substrate, the via containing aconductive material; a second electrode layer formed over the firstprincipal surface of the substrate, the second electrode beingelectrically connected to the conductive layer by means of theconductive material in the via.
 2. The capacitor of claim 1 wherein thedoping concentration of the semiconductor substrate is greater than1×10¹⁹ cm⁻³.
 3. The capacitor of claim 1 wherein the thickness of thesemiconductor substrate is less than 200 microns.
 4. The capacitor ofclaim 1 wherein the dielectric layer comprises an oxide.
 5. Thecapacitor of claim 1 wherein the thickness of the dielectric layer isgreater than or equal to 0.005 micron.
 6. The capacitor of claim 1further comprising a passivation layer overlying the first and secondelectrodes, a first opening being formed in the passivation layer overthe first electrode and a second opening being formed in the passivationover the second electrode.
 7. The capacitor of claim 6 comprising afirst metal ball in the first opening and a second metal ball in thesecond opening, the first metal ball being electrically connected to themain electrode layer, the second metal ball being electrically connectedto the second electrode layer.
 8. An ESD-protected capacitor arrangementcomprising the capacitor of claim 1 in combination with a pair ofoppositely-directed diodes, the oppositely-directed diodes beingconnected in parallel with the capacitor and being formed in thesubstrate.
 9. The ESD-protected capacitor arrangement of claim 8 whereinthe substrate is doped with material of a first conductivity type andthe pair of diodes comprise: a first region of the first conductivitytype in electrical contact with the main electrode layer; and a secondregion of a second conductivity type adjacent to the first region andforming a first PN junction with the first region.
 10. The ESD-protectedcapacitor arrangement of claim 9 comprising a third region the firstconductivity type adjacent to the second region and forming a second PNjunction with the second region.
 11. A precision high-frequencycapacitor comprising: a heavily-doped semiconductor substrate havingfirst and second principal surfaces; a first dielectric layer portionformed on the first principal surface of the substrate; a firstelectrode layer formed on the first dielectric layer portion andelectrically insulated from the substrate; a second dielectric layerportion formed the first principal surface of the substrate; and asecond electrode layer formed on the second dielectric layer portion,the second electrode layer being electrically insulated from thesubstrate and the first electrode layer.
 12. The capacitor of claim 11wherein the doping concentration of the semiconductor substrate isgreater than 1×10¹⁹ cm⁻³.
 13. The capacitor of claim 11 wherein thedielectric layer portions comprise an oxide.
 14. The capacitor of claim11 wherein the thickness of the dielectric layer portions is greaterthan or equal to 0.005 micron.
 15. The capacitor of claim 11 furthercomprising a passivation layer overlying the first and secondelectrodes, a first opening being formed in the passivation layer overthe first electrode and a second opening being formed in the passivationlayer over the second electrode.
 16. The capacitor of claim 15comprising a first metal ball in the first opening and a second metalball in the second opening, the first metal ball being electricallyconnected to the main electrode layer, the second metal ball beingelectrically connected to the second electrode layer.
 17. The capacitorof claim 11 comprising a trench in the substrate beneath the firstdielectric layer portion, the first dielectric layer portion extendingalong the walls of the trench, the trench containing a conductivematerial, the conductive material being in electrical contact with thefirst electrode.
 18. The capacitor of claim 17 wherein the dielectriclayer portions comprise an oxide.
 19. The capacitor of claim 17 whereinthe conductive material comprises polysilicon.
 20. The capacitor ofclaim 17 further comprising a passivation layer overlying the first andsecond electrodes, a first opening being formed in the passivation layerover the first electrode and a second opening being formed in thepassivation layer over the second electrode.
 21. The capacitor of claim20 comprising a first metal ball in the first opening and a second metalball in the second opening, the first metal ball being electricallyconnected to the main electrode layer, the second metal ball beingelectrically connected to the second electrode layer.
 22. The capacitorof claim 11 wherein the first electrode layer comprises a firstplurality of fingers and the second electrode layer comprises a secondplurality of the fingers, the first and second pluralities of fingersbeing interdigitated.
 23. The capacitor of claim 22 wherein the firstplurality of fingers extend from a first palm portion of the firstelectrode layer portion, the first dielectric layer portion beingthinner under the first plurality of fingers than under the first palmportion.
 24. The capacitor of claim 23 wherein the second plurality offingers extend from a second palm portion of the second electrode layerportion, the second dielectric layer portion being thinner under thesecond plurality of fingers than under the second palm portion.
 25. Aprecision high-frequency capacitor comprising: a heavily-dopedsemiconductor substrate having first and second principal surfaces; adielectric layer formed on the first principal surface of the substrate;a first electrode layer formed on the dielectric layer and electricallyinsulated from the substrate; and a second electrode layer formed on thefirst principal surface of the substrate, the second electrode layerbeing in electrical contact with the substrate.
 26. The capacitor ofclaim 25 further comprising a passivation layer overlying the first andsecond electrodes, a first opening being formed in the passivation layerover the first electrode and a second opening being formed in thepassivation layer over the second electrode.
 27. The capacitor of claim26 comprising a first metal ball in the first opening and a second metalball in the second opening, the first metal ball being electricallyconnected to the main electrode layer, the second metal ball beingelectrically connected to the second electrode layer.
 28. The capacitorof claim 25 wherein the first electrode layer comprises a firstplurality of fingers and the second electrode layer comprises a secondplurality of the fingers, the first and second pluralities of fingersbeing interdigitated.
 29. The capacitor of claim 28 wherein the firstplurality of fingers extend from a first palm portion of the firstelectrode layer portion, the first dielectric layer portion beingthinner under the first plurality of fingers than under the first palmportion.
 30. A method of fabricating a capacitor in a semiconductorsubstrate having first and second principal surfaces, comprising:forming a dielectric layer on the first principal surface of thesubstrate; forming a conductive layer on the second principal surface ofthe substrate; cutting a via through the substrate from the firstprincipal surface to the conductive layer; depositing a conductivematerial into the via; forming an electrode layer over the first surfaceof the substrate; and patterning the electrode layer to form first andsecond portions, the first portion being insulated from the substrate bythe dielectric layer, the second portion being in electrical contactwith the conductive material in the via.